library verilog;
use verilog.vl_types.all;
entity uart is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        din_tx          : in     vl_logic_vector(7 downto 0);
        din_vld_tx      : in     vl_logic;
        din_rx          : in     vl_logic;
        dout_rx         : out    vl_logic_vector(7 downto 0);
        dout_vld_rx     : out    vl_logic;
        rdy_tx          : out    vl_logic;
        dout_tx         : out    vl_logic
    );
end uart;
